Continuous-time analog-to-digital converters (CT ADCs) and continuous-time digital-to-analog converters (CT DACs) are distinguished from their discrete-time counterparts (DT ADCs and DT DACs) in that sampling is not used in their front-end circuitry. Rather, in the case of a continuous-time ADC, some form of filtering or analog processing is employed prior to sampling (or storing) the input waveform as part of the eventual digitization. In the case of the continuous-time DAC, no sampling is used. This continuous-time approach has several advantages as compared to using a discrete-time converter. For example, two benefits of using continuous-time ADC or DAC are reduced sensitivity to coupled noise and the potential for lower power implementations.
The power and noise sensitivity benefits of continuous-time converters can be understood by comparing and contrasting their performance with that of a discrete-time converter. FIG. 1A shows an example of a conventional discrete-time DAC. The discrete-time DAC is implemented using a switched-capacitor (S-C) strategy. Depending on the DAC input code, certain capacitors on the left (CIN1, CIN2, . . . CINn) are first charged to a reference voltage VREF. While the selected input capacitors are being charged to VREF, an integrating capacitor CFB placed between the output of an amplifier A1 and its inverting terminal, is reset by closing a switch S1. Next, the charge stored on the selected input capacitors is transferred to the capacitor CFB when the selected input capacitors are connected between the inverting (“−”) terminal of the amplifier A1 and ground. Because the input capacitors are selected by the digital input to the DAC, the magnitude of the charge that is transferred to the capacitor CFB, and therefore the voltage across it, is also dependent on the input code to the DAC. A sample-and-hold (S/H) circuit can be placed after the amplifier A1 in order to hold the output value from the amplifier A1 during settling and reset.
FIG. 1B shows a conventional continuous-time DAC implementation using a current DAC (IDAC). Positive and negative weighted current sources (I1p, I1n, I2p, I2n, . . . Inp, Inn) are selected as mapped from a given DAC code. Each selected current is connected to the inverting input of an amplifier A2. The amplifier stage is configured as a low-pass trans-impedance stage with a feedback resistor RFB connected in parallel with a feedback capacitor CFB. The feedback resistor RFB then develops a voltage proportional to the total current connected to the inverting terminal of the amplifier A2. Since the input currents are selected by the input DAC code, there is a direct mapping from the input code to its output voltage. The capacitor CFB provides the aforementioned low-pass characteristic of the stage by smoothing the output voltage transitions as DAC codes are changed.